AED702 - Introduction to ASIC Development Principles

Subject Title
Introduction to ASIC Development Principles

Subject Description
This course is a introductory course covering aspects of Full custom Integrated Circuit cell layout in relation to standard cell circuit design.

A background review of the CMOS process, MOS model, CMOS logic gates will complement lab work will focus on translating schematics based upon standard cells to layout using both the Mentor and Cadence tool set.

Credit Status
One subject credit in the Applied Electronics Design Program

Learning Outcomes
Upon successful completion of this subject the student will be able to:

Recognize basic building blocks of CMOS circuits, CMOS cross sections, translation of of schematics to layout (relations of layers, folding of gates, sharing of diffusions, dimensioning of metal lines/power considerations, use of arrays, concept of fix sized vias), Reliability issues with layout (latchup, ESD and current diversion) and efficient layout techniques (use of grids, hiearchy).

The second focus is to familiarize the student with 1st order behaviour of devices, digital gates and interconnect to geometry and process. Transistor level simulators such as SPICE/HSPICE will be used as a virtual lab environment to validate the 1st order models of device and digital circuit behaviour.

The third outcome will be a project on the complexity of an 4 bit adder will use and illustrate the above principles will be done in groups of three. Presentations will follow at the end of the course. Designs will be manually routed and created using library elements created earlier in the course. A comparison with an "place and route" tool will be made.

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